1. Field of the Invention
The present invention relates to a reconfigurable integrated circuit capable of determining a circuit configuration by selecting connection relationship between function blocks.
2. Description of Related Art
As a processor unit for executing various data processes, products called CPU (Central Processing Unit) and MPU (Micro Processor Unit) are coming into practical use. In a data processing system using these processor units, an application program including several instructions and processing data are stored in a memory device. The processor unit reads out the instructions and processing data from the memory device to sequentially execute operations. Such processor unit is able to achieve various data processes by switching application programs. However complicated data processes cannot be executed at high speed as the instructions and processing data are sequentially read out from the memory device to be executed.
On the other hand, a dedicated circuit manufactured using cell-based IC and gate array is referred to as a custom IC and ASIC (Application Specific Integrated Circuit) or the like. As in such dedicated circuit, since a logical circuit for executing data processes is formed by hardware, complicated data processes can be executed at high speed. However the dedicated circuit has a disadvantage that it can be used only for particular data processes and is lacking flexibility as compared to the abovementioned data processing system including CPU.
As a middle device between them, a reconfigurable device is known that is capable of changing circuit configuration depending on the application program or processing data. In the reconfigurable device, various operation units and register files are provided as many small-sized function blocks. Further, in a design or operation of a device, the circuit configuration of the reconfigurable device can be changed by changing operation and connection relationship of the function blocks depending on the application program or processing data.
The configuration of a general reconfigurable device 7 is shown in FIG. 22. A function block 70 includes one or a plurality of operation units and register files. A programmable switch (PSW) 15 is provided to lines for connecting between several function blocks 70 and connected to wiring resource for connecting between the function blocks 70 and to input/output ports of function blocks 70. By the control of the programmable switches 15, connections between the function blocks 70 can be switched. As configuration information memories (CFGM) 16 enables to change the configuration of the reconfigurable device 7, they store configuration information regarding the operation of the function blocks 17 and connection relationship of the programmable switches 15 that is required for configuration definition of the reconfigurable device 7. The circuit configuration can be changed by loading the configuration information stored in the configuration memory 16 to the function blocks 70 and programmable switches 15 depending on application programs or processing data.
An array processor, which is one of the abovementioned reconfigurable devices, is disclosed in Japanese Unexamined Patent Application Publication No. 2001-312481 and No. 2003-76668. Hereinafter, the array processor disclosed in Japanese Unexamined Patent Application Publication No. 2001-312481 and No. 2003-76668 is referred to as a first related art. The array processor of the first related art is described with reference to FIGS. 23 to 25.
FIG. 23 shows a configuration example of an array processor 8 according to the first related art. The array processor 8 has a configuration in which processor elements (PE) 81 and programmable switches 15 for electrically connecting among the processor elements (PE) 81 being arranged in matrix. Further, the array processor 8 includes a State Transition Controller (STC) 82 for controlling changes of a circuit configuration by changes in transitions of processing state of the array processor 8, which is specifically the changes in operation of the processor elements 81 and connection relationship between the processor elements 81.
The STC 82 holds a series of object codes being input externally, generates an instruction pointer (IP) for the processor elements 81 and programmable switches 15 and supplies the generated instruction pointer to the processor elements 81 and programmable switches 15. The instruction pointer here is information for specifying an address of an instruction code stored in an instruction memory 801, which is described later in detail. Further, an instruction code is an identifier for specifying the operation of the processor elements 81 and wiring connections by the programmable switches 15. Specifically, the instruction memory 801 corresponds to the configuration memory 16 and an instruction code corresponds to configuration information stored in the configuration memory 16.
The configuration of the processor element 81 is shown in FIG. 24. The processor element 81 includes operation units such as the instruction memory 801, an instruction decoder 802, register file 140, ALU (Arithmetic and Logical unit) 803, which is an operation unit for performing arithmetic and logic operations) and DMU (Data Management Unit) 804, which is an operation unit with functions such as bit processes. Further, an internal wiring resource 805 is a programmable switch for changing data input destination for data input from the programmable switch 15 and connection relationship between the operation units including the register file 140 and ALU 803.
The instruction memory 801 stores an instruction code for defining operations such as a selection of the operation units in the processor element 81. The instruction decoder 802 decodes the instruction code and controls the operations of the operation units including the ALU 803 and internal wiring resource 805. The instruction memory 801 is able to store a plurality of instruction codes and dynamically change the circuit configuration of the array processor 8 by switching an instruction pointer supplied from the STC 82 to the instruction memory 801.
An example of internal configuration for the ALU 803 is shown in FIG. 25. The ALU 803 includes two data input ports 8031 and 8032 and a data output port 8034. A bit wide of input/output data for these ports is m bit, which is a data processing unit in the array processor 8. Further, the ALU 803 includes a 2-input logic operation unit 128, 2-input selector 129, 2-input m bit wide adder/subtracter 126 and 2-input m bit wide comparator 127 connected in parallel between the input port 8031 and 8032 and output port 8034. A multiplexer 131 is provided between the operation units 127 to 129 and output port 8034. An output from one of the operation units 127 to 129 is selected by the multiplexer 131 and output to the output port 8034.
In response to the instruction code supplied to the ALU 803 via the instruction decoder 802, by selecting the operation units 127 to 129 and input source for the multiplexer 131, the ALU 803 operates as various arithmetic operation units, logic operation unit, selector or comparator.
As described above, the array processor 8 includes a plurality of function blocks including the ALU 803 inside the processor element 81 and the internal wiring resource 805 for switching the connection between the function blocks. The array processor 8 further includes the programmable switches 15 for switching the connection between the processor elements 81. To be more specific, as against to the configuration of the reconfigurable device 7 shown in FIG. 22 in which the function blocks 70 are variably connected through the programmable switches 15, the array processor 8 has a hierarchized configuration by variable connections between the function blocks inside the processor elements 81 and variable connections between the function blocks between the processor elements 81.
The abovementioned reconfigurable device 7 and array processor 8 have an advantage of having better flexibility in the circuit configuration as compared to dedicated circuits such as ASIC and also have a disadvantage of having redundant reconfigurable circuit configuration. The reconfigurable device 7 and array processor 8 have a plurality of function blocks 70 and processor elements 81 that support for switching the circuit configuration, configuration memory 16 for storing circuit configuration information or instruction memory 801 and instruction decoder 802. Further, the programmable switches 15 for switching the connection relationship between the function blocks or processor elements require larger wiring area as compared to a wiring for the dedicated circuits. Therefore, to form a desired circuit by the reconfigurable device 7 or array processor 8, an integration degree is lower as compared to when forming the same circuit by a dedicated circuit, thereby reducing an area efficiency.
As an example, a comparison when a circuit for performing arithmetic operation of (A+B)*(C+D)→Y is formed by the reconfigurable device 7 and a dedicated circuit is shown in FIGS. 26A and 26B. FIG. 26A shows a circuit formed by the dedicated circuit. The circuit of FIG. 26A is comprised of an adding circuit 810a for calculating A+B, adding circuit 810b for calculating C+D and a multiplying circuit 811 for multiplying output data from the two adding circuits. On the other hand, FIG. 26B shows the configuration by the reconfigurable device 7. In such case, in addition to components which are programmable switches 15a to 15c for enabling to switch input data to function blocks 70a to 70c and operation units required to comprise the adding and multiplying circuits, other circuit components included in the function blocks 70a to 70c and configuration information memories 16a to 16c are required. Other circuit components included in the function blocks 70a to 70c and the configuration information memories 16a to 16c are redundant part when forming the circuit by the reconfigurable device 7.
Reconfigurable devices according to the related art including the abovementioned array processor 7 may not be able to achieve an efficient circuit in terms of area efficiency and processing speed, depending on content of application program and processing data.
As an example, a case is described in which the number of inputs to the function block 70 of the reconfigurable device 7 is increased in order to efficiently process multi-inputs that exceeds 2-input. FIG. 27 shows an example in which the function block 70 is made to be a function block for 4-input. The function block 70 shown in FIG. 27 includes a 4-input operation unit 110. Input data is supplied from four input ports 104a to 104d to the 4-input operation unit 110 and the operation result by the 4-input operation unit 110 is output from an output port 105 of the function block 70.
Increased number of inputs to the function block 70 is advantageous in light of improving operation speed. For example to realize a 4-input selector by a 2-input function block, three function blocks having 2-input selectors are required. As the connection between the function blocks are performed via a programmable switch, an operation speed is reduced due to signal delay in the programmable switch and wiring. On the other hand, when using the function block of 4-input shown in FIG. 27, it is possible to avoid reducing the operation speed caused from accumulation of wiring delays.
However increased number of input ports to the function block 70 in the reconfigurable device 7 results to increase the size of the programmable switch 15 for selecting input source for the input ports and configuration memory 16. In the case of FIG. 27, if the input ports to the function block 70 increases from 2-input to 4-input, the size of input selection unit 151 included in the programmable switch 15 doubles as compared to 2-input. This is because that the input source for the input ports 104a to 104d can be selected. Further, the size of the configuration memory 16 for storing configuration information of the input selection units 151a to 151d doubles as compared to 2-input.
Furthermore, this applies to addition and subtraction of data exceeding m bit. To add/subtract data exceeding m bit by combining m bit adder/subtracter, specifically to add/subtract with carry, a carry propagate is required between the m bit adder/subtracters. Therefore the plurality of function blocks 70 must be connected via the programmable switches 15 and this causes to reduce the operation speed due to wiring delays.
Thus as shown in FIG. 28, the adder/subtracter in the function block 70 is referred to as a 2 m bit wide adder/subtracter 122 that divides two 2m bit input data each into upper m bit and lower m bit and input from the four input ports 104a to 104d having m bit wide. Further, output data from the 2 m bit wide adder/subtracter is divided into upper m bit and lower m bit and output from output ports 105a and 105b. With this configuration, a carry propagate between the function blocks is unnecessary while using the programmable switch 15 having m bit wide and wiring resource.
However, as with the configuration to achieve the abovementioned 4-input selector, along with the increase of the number of input ports to the function block 70, size of the programmable switch 15 for selecting and configuration memory 16 also increases. Accordingly this increases hardware size of the reconfigurable device. The increase in the hardware size of the reconfigurable device causes to reduce integration degree of the reconfigurable device and further reduce area efficiency.
Note that even with increased number of input ports to the function block 70, by restricting the number of inputs of the programmable switch 15, it is possible to restrain from increasing the size of the programmable switch 15 and configuration memory 16. However in this way, flexibility of wiring between the function blocks 70 is limited, thereby constraining flexibility of changing circuit configuration.
As described above, we have now discovered a problem in the reconfigurable device according to the first related art in which along with the increase in the input port to the function block, the size of the programmable switch and configuration memory increases and the hardware size also increases.
Incidentally, such problem exists not only in the array processor 8 which is able to dynamically reconfigure depending on the application program. Specifically, this problem is common to reconfigurable integrated circuits having a configuration in which a connection relationship between function blocks are determined by a programmable switch such as a reconfigurable device capable of changing a connection relationship between function blocks including PLD (Programmable Logical Device) and FPGA (Field Programmable Gate array).